Leakage Current in GaN HEMTs Explained: Causes, Effects, Measurement and Reduction Techniques

GaN Power Electronics Masterclass – Part 32

This lesson is part of the Complete GaN Power Electronics Masterclass.

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Leakage Current in GaN HEMTs: Causes, Effects, Measurement and Reduction Techniques


Table of Contents

  • Introduction
  • What is Leakage Current?
  • Why Leakage Current Matters in GaN HEMTs
  • Types of Leakage Current
  • Gate Leakage Current
  • Drain Leakage Current
  • Buffer Leakage Current
  • Surface Leakage Current
  • Causes of Leakage Current
  • Effect of Temperature
  • Effect on Reliability
  • Measurement Methods
  • Leakage Current Reduction Techniques
  • Comparison with Silicon and SiC Devices
  • Applications
  • Future Trends
  • Frequently Asked Questions
  • Conclusion

Introduction

Gallium Nitride High Electron Mobility Transistors are widely used in high-efficiency power electronics because they offer fast switching speed, low gate charge, low output capacitance, high electron mobility, and high power density. However, like every semiconductor device, GaN HEMTs are not perfect switches. Even when the device is supposed to be OFF, a small unwanted current can still flow through different leakage paths. This unwanted current is called leakage current. Leakage current may look small compared with normal operating current, but it has a major effect on high-voltage blocking capability, standby power loss, thermal stress, long-term reliability, gate stability, and converter safety. In high-density converters, EV onboard chargers, AI data center power supplies, telecom converters, and renewable energy systems, leakage current must be carefully controlled.

Key Takeaway Leakage current in GaN HEMTs is the unwanted current that flows when the device is OFF or when the gate should be blocking current. It can occur through the gate, drain, buffer, or surface and directly affects efficiency, reliability, and breakdown performance.

What is Leakage Current?

Leakage current is the small current that flows through a semiconductor device even when the device is intended to block current. In an ideal switch, OFF-state current should be zero. In a real GaN HEMT, material defects, surface traps, high electric fields, imperfect barriers, and temperature effects allow a small amount of current to flow.


Ideal OFF-State Device:

VDS Applied
Gate OFF
Current = 0


Real GaN HEMT:

VDS Applied
Gate OFF
Small Leakage Current Flows

The leakage current may flow vertically through the buffer, laterally across the surface, through the gate junction, or between drain and source depending on the device structure and applied voltage.


Why Leakage Current Matters in GaN HEMTs

Leakage current is not just a minor parasitic effect. In practical power electronics, it influences several important design parameters.

  • It increases OFF-state power loss.
  • It reduces breakdown voltage margin.
  • It increases device temperature.
  • It may indicate material defects or trap-related problems.
  • It affects long-term reliability.
  • It can create false triggering in sensitive gate-drive circuits.
  • It reduces converter standby efficiency.
  • It can accelerate degradation under high-voltage stress.

Types of Leakage Current in GaN HEMTs

Leakage current in GaN HEMTs can be divided into several categories depending on the current path.

Leakage Type Main Path Main Cause
Gate Leakage Gate to channel or gate to source/drain Schottky barrier leakage, dielectric defects, gate stress
Drain Leakage Drain to source in OFF state High electric field, traps, punch-through
Buffer Leakage Through GaN buffer layer Defects, incomplete isolation, high-voltage stress
Surface Leakage Across device surface Surface states, contamination, passivation quality
Substrate Leakage Through substrate or transition layer Substrate conductivity and buffer design

Gate Leakage Current

Gate leakage current is the unwanted current that flows through the gate terminal. It is especially important in Schottky-gate GaN HEMTs because the gate forms a metal-semiconductor junction rather than a fully insulated oxide gate. In p-GaN gate devices and MIS-HEMTs, gate leakage is generally lower, but it can still occur due to defects, high electric field stress, dielectric traps, or excessive gate voltage.

Main Causes of Gate Leakage

  • Schottky barrier tunneling.
  • Gate dielectric defects.
  • Excessive positive gate voltage.
  • Trap-assisted conduction.
  • High temperature operation.
  • Process-induced damage under the gate.

Effects of Gate Leakage

  • Increases gate-drive power loss.
  • Reduces gate voltage stability.
  • Can damage the gate region over time.
  • May cause threshold voltage shift.
  • Reduces long-term reliability.

Drain Leakage Current

Drain leakage current flows between drain and source when the GaN HEMT is in the OFF state and high drain voltage is applied. This is one of the most important leakage parameters for power devices because the device must safely block high voltage during operation.

Drain leakage generally increases with drain-to-source voltage, temperature, electric field concentration, and defect density.

Common Causes of Drain Leakage

  • High electric field near the gate edge.
  • Surface traps between gate and drain.
  • Buffer layer defects.
  • Insufficient gate-to-drain spacing.
  • Poor passivation.
  • Edge termination issues.

Buffer Leakage Current

Buffer leakage occurs when current flows through the GaN buffer layer instead of staying confined to the 2DEG channel. Since the buffer layer supports high-voltage blocking, poor buffer design can significantly reduce breakdown voltage and increase OFF-state current.

Modern GaN power devices often use carbon-doped or iron-doped buffer layers to improve isolation and reduce leakage. However, excessive traps in the buffer can also contribute to dynamic RDS(on) and current collapse.

Engineering Insight Buffer design is a compromise. A highly resistive buffer reduces leakage current, but trap-rich buffer layers may increase dynamic RDS(on). Good GaN device design must balance leakage suppression and switching performance.

Surface Leakage Current

Surface leakage current flows along the semiconductor surface, especially between gate and drain where the electric field is high. It is strongly influenced by surface quality, contamination, passivation, and trapped charges.

Methods to Reduce Surface Leakage

  • High-quality silicon nitride passivation.
  • Surface cleaning before dielectric deposition.
  • Field plate design.
  • Reduced surface trap density.
  • Optimized gate-to-drain spacing.

Causes of Leakage Current

Cause Explanation
Crystal Defects Dislocations and vacancies create leakage paths.
Surface Traps Trap-assisted conduction increases surface leakage.
High Electric Field Strong fields increase tunneling and impact ionization.
Poor Passivation Unprotected surfaces are more sensitive to leakage.
Gate Stress Excessive voltage damages gate barriers.
Temperature Rise Thermal energy increases carrier generation.
Buffer Defects Incomplete isolation allows vertical leakage.

Temperature Effect on Leakage Current

Leakage current generally increases with temperature. As temperature rises, more carriers gain enough thermal energy to cross barriers or participate in trap-assisted conduction. This is why high-temperature testing is important for GaN device reliability.


Temperature Increases

↓

Carrier Energy Increases

↓

Trap-Assisted Conduction Increases

↓

Gate / Drain / Buffer Leakage Increases

↓

Reliability Margin Reduces


Effect of Leakage Current on Reliability

Leakage current is often used as an early indicator of device degradation. A gradual increase in leakage during stress testing may indicate gate damage, dielectric degradation, buffer instability, or surface trap activation.

  • Increased leakage raises junction temperature.
  • Higher temperature accelerates degradation.
  • Gate leakage may lead to gate failure.
  • Drain leakage reduces blocking capability.
  • Buffer leakage may cause premature breakdown.
  • Surface leakage may increase current collapse.

How Leakage Current is Measured

Leakage current is usually measured using a semiconductor parameter analyzer or curve tracer. The device is biased in the OFF state while current is measured at the gate, drain, or substrate terminal.

Measurement Bias Condition Measured Current
Gate Leakage Apply VGS, keep drain controlled IGSS
Drain Leakage Gate OFF, apply VDS IDSS
Buffer Leakage High drain bias, substrate/buffer monitored Vertical leakage current
Surface Leakage High gate-to-drain field Lateral leakage current

Leakage Current Reduction Techniques

  • Use high-quality epitaxial GaN layers.
  • Optimize buffer doping and thickness.
  • Improve surface passivation.
  • Use field plates to reduce electric field peaks.
  • Optimize gate-to-drain spacing.
  • Reduce plasma etch damage during fabrication.
  • Use high-quality gate dielectrics in MIS-HEMTs.
  • Control gate voltage carefully using proper gate drivers.
  • Improve substrate isolation.
  • Use advanced edge termination structures.

GaN vs Silicon vs SiC Leakage Behavior

Parameter Silicon MOSFET SiC MOSFET GaN HEMT
OFF-State Leakage Low to Moderate Low Depends strongly on buffer and surface quality
Gate Leakage Very Low due to oxide gate Very Low due to oxide gate Can be higher in Schottky gate, lower in p-GaN/MIS structures
Temperature Sensitivity Moderate Low to Moderate Moderate; depends on device design
Surface Trapping Effect Lower Moderate Important design concern
High-Frequency Suitability Limited Good Excellent

Applications Where Leakage Current Matters

  • AI data center power supplies.
  • Electric vehicle onboard chargers.
  • Fast DC chargers.
  • High-voltage DC-DC converters.
  • Renewable energy inverters.
  • Telecommunication power supplies.
  • Aerospace power electronics.
  • Battery energy storage systems.
  • Medical power supplies.
  • Low-standby-power adapters.

Future Trends

  • Lower-defect GaN epitaxy.
  • Advanced carbon-doped buffer structures.
  • Improved p-GaN gate reliability.
  • High-k dielectric MIS-HEMTs.
  • Better passivation materials.
  • AI-assisted leakage prediction.
  • Wafer-level reliability screening.
  • Vertical GaN structures with better leakage control.
  • Advanced thermal packaging.

Frequently Asked Questions (FAQs)

What is leakage current in GaN HEMTs?

Leakage current is the unwanted current that flows through the gate, drain, buffer, surface, or substrate when the GaN HEMT is supposed to be OFF or blocking voltage.

Why does leakage current occur in GaN devices?

It occurs due to high electric fields, crystal defects, surface traps, imperfect passivation, gate barrier leakage, buffer defects, and temperature effects.

Is gate leakage higher in GaN than silicon MOSFETs?

Schottky-gate GaN devices may show higher gate leakage than oxide-gate silicon MOSFETs. However, p-GaN and MIS-HEMT structures significantly reduce gate leakage.

How does temperature affect leakage current?

Higher temperature generally increases leakage current because more carriers gain enough energy to cross barriers or move through trap-assisted paths.

How can leakage current be reduced?

Leakage can be reduced through better epitaxial quality, optimized buffer design, high-quality passivation, improved gate dielectric, field plates, proper gate-driver voltage control, and optimized device geometry.

Why is leakage current important in power converters?

It affects standby loss, thermal stress, voltage blocking capability, reliability, efficiency, and long-term device lifetime.


Conclusion

Leakage current is one of the most important reliability and performance parameters in GaN HEMTs. Although GaN devices provide excellent switching speed, high electron mobility, and high power density, their leakage behavior must be carefully controlled through material quality, device design, passivation, gate engineering, and proper circuit operation. Gate leakage, drain leakage, buffer leakage, and surface leakage each have different causes and require different mitigation techniques. By improving epitaxial growth, reducing defects, optimizing field plates, and using advanced gate structures such as p-GaN and MIS-HEMT designs, engineers can significantly improve the leakage performance of GaN power devices. As GaN technology moves deeper into EV chargers, AI data centers, aerospace systems, and renewable energy converters, leakage current control will remain essential for achieving high efficiency, high voltage reliability, and long service life.



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